The present invention is generally related with a novel design of PMOS SRAM based NVRAM cell structure and array for an extremely fast Write (Program and Erase) speed, which only requires the low-voltage VDD and VSS for Program and Program-Inhibit operations for an extremely high-density, low-current, in-circuit programmable and erasable NVSRAM and SRAM-based field-programmable gate array (FPGA) designs.
The CMOS NVSRAM is well known for years in the art. Typically, it comprises a 6T SRAM cell and a Flash cell. During the read operation, Flash is isolated from SRAM and is transparent to the SRAM users. But the SRAM lacks of permanent storage capability after the normal power off or the unexpected power loss. Therefore, there is a need to back up all data that is being stored in all on-chip volatile SRAM into the nonvolatile Flash on the same die within a very short period of time. NVSRAM prevails over NVDRAM in market place because it does not consume any power as NVDRAM for the data refreshment during the read operation.
Three prior arts related to NVSRAM cells are referred to for this application, including a U.S. Pat. No. 7,164,608 related to 1-poly NVSRAM, a U.S. Pat. No. 7,760,540 (filed by a same inventor as the present application and commonly assigned) related to 2-poly NVSRAM, and a U.S. patent application Ser. No. 13/888,134 (filed by the same inventor of the present application) related to low voltage fast-write NVSRAM cell.
All these prior works are actually related to the NMOS NVSRAM cell because they uses NMOS flash transistor as the storage NVM transistor, regardless of 1-poly charge trapping SONOS type or 2-poly floating-gate type flash cell. Although the NMOS NVSRAM cells have many advantages, there is one severe drawback which is the reverse of the polarity of stored data between each SRAM and each Flash cell in each NVSRAM cell after program operation of each NMOS NVSRAM. As a result, during the power-up period, the downloading of each Flash data into each corresponding SRAM cell needs more complicate circuit handling technique to make it into the same data polarity. Or as in the U.S. patent application Ser. No. 13/888,134, more transistors were added to eliminate the reverse polarity with a simple write circuit but at the sacrifice of larger silicon area overhead.
Therefore, an improved PMOS NVSRAM cell design and associated operations are needed and become objectives of the present invention.